I'm Riyane (Purpose), a 22-year-old software engineer focused on the intersection of hardware and software. I build systems where performance isn't a feature, but the specification. I care about what the CPU actually does, not what the abstraction promises.
- 🔭 Currently: Hardening Tachyon (C++ IPC)
- 😄 Pronouns: He/Him
- 📫 Reach me:
- 🤖 Discord:
purpose.dev - 📧 Email:
[email protected]
- 🤖 Discord:
- Low-Latency Systems: Lock-free SPSC/MPMC, memory barriers, and cache-line alignment to eliminate false sharing.
- Modern C++ & Assembly: Leveraging C++26 and x86-64 Assembly to own the hardware path and minimize instruction retirement latency.
- Deterministic Software: Building systems without GC pauses, heap allocations on the hot path, or unnecessary kernel overhead.
- High-Performance Computing: CUDA kernels, async DMA pipelines, and SIMD vectorization for massive data throughput.
- Security Analysis: Low-level research into EVM storage layout, slot collisions, and DeFi protocol logic.
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Systems & Low-Level:
- Languages: C++17-26, C, x86 Assembly, CUDA, Zig.
- Primitives: Atomics (
acquire/release), Futex,memfd_create(sealing), Huge Pages, CPU Pinning. - Tools:
perf, Valgrind/Sanitizers (ASan, TSan), LibFuzzer, PGO/LTO.
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HFT & IPC:
- Transport: Tachyon
- Primitives: Cache-aligned descriptors, shadow indices, lock-free ring buffers.
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HPC & Storage:
- Engines: ClickHouse, PostgreSQL, Redis.
- Data: DLPack (zero-copy tensor sharing), Protobuf, Apache Avro.
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JVM Ecosystem:
- Languages: Java, Scala.
- Techniques: Off-heap buffer management, zero-GC query paths via JNI, lock-striped LRU page managers.