Jekyll2020-04-08T04:58:46-05:00https://tymonx.com/feed.xmlFPGA power!Professional FPGA and Embedded Systems DesignTymoteusz Blazejczykcontact@tymonx.comWelcome to tymonx.com site!2020-03-25T10:51:39-05:002020-03-25T10:51:39-05:00https://tymonx.com/update/2020/03/25/welcome-to-tymonx.com-site<p>Welcome to <a href="https://tymonx.com">tymonx.com</a> site!</p>
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<figure class="highlight"><pre><code class="language-verilog" data-lang="verilog"><span class="k">always_ff</span> <span class="o">@</span><span class="p">(</span><span class="kt">posedge</span> <span class="n">tx</span><span class="p">.</span><span class="n">clk</span> <span class="kt">or</span> <span class="kt">negedge</span> <span class="n">tx</span><span class="p">.</span><span class="n">reset</span><span class="p">)</span> <span class="k">begin</span>
<span class="k">if</span> <span class="p">(</span><span class="n">tx</span><span class="p">.</span><span class="n">is_reset</span><span class="p">())</span> <span class="k">begin</span>
<span class="n">tx</span><span class="p">.</span><span class="n">valid</span> <span class="o"><=</span> <span class="mb">'0</span><span class="p">;</span>
<span class="k">end</span>
<span class="k">else</span> <span class="k">begin</span>
<span class="n">tx</span><span class="p">.</span><span class="n">set</span><span class="p">(</span><span class="n">rx</span><span class="p">.</span><span class="n">get</span><span class="p">());</span>
<span class="k">end</span>
<span class="k">end</span></code></pre></figure>Tymoteusz Blazejczykcontact@tymonx.comWelcome to tymonx.com site!