Stars
ASIC implementation flow infrastructure, successor to OpenLane
Digital HDL Design Full-stack Agents
open source hardware synthesis. SystemVerilog, VHDL and ABEL-HDL to gate-level netlists
Run OpenClaw more securely inside NVIDIA OpenShell with managed inference
A lightweight alternative to OpenClaw that runs in containers for security. Connects to WhatsApp, Telegram, Slack, Discord, Gmail and other messaging apps,, has memory, scheduled jobs, and runs dir…
Natural Language Exploration of Hardware Designs and Libraries (ICLAD'25) -- Best Paper Award
The SBOM tool is a highly scalable and enterprise ready tool to create SPDX 2.2 compatible SBOMs for any variety of artifacts.
A fast VHDL language server and analysis library written in Rust
Claude Opus 4.6 wrote a dependency-free C compiler in Rust, with backends targeting x86 (64- and 32-bit), ARM, and RISC-V, capable of compiling a booting Linux kernel.
Use graph neural network to predict power, timing and area of a digital system.
LEC - Logic Equivalence Checking - Formal Verification
A Verilog synthesis flow for Minecraft redstone circuits
A machine learning accelerator core designed for energy-efficient AI at the edge.
CRCat: Complex Rational Catalog of all Possible RLC Networks of up to and Including Five Elements
Manage headless displays with Xvfb (X virtual framebuffer)
TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)
A SystemVerilog language server based on the Slang library.
TensorZero is an open-source LLMOps platform that unifies an LLM gateway, observability, evaluation, optimization, and experimentation.
akashlevy / OpenRRAM
Forked from VLSIDA/OpenRAMAn open-source resistive random access memory (RRAM) compiler based on OpenRAM.
Evaluating accuracy on quantized DNNs using RRAM as weight storage