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1. bazel_rules_hdl bazel_rules_hdl Public

   Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

   Starlark 156 63

2. constraints constraints Public

   Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards

   Tcl 48 11

3. packages packages Public

   Repo to help explain the different options users have for packaging.

   19

4. awesome awesome Public

   A curated list of awesome resources for HDL design and verification

   Shell 172 22

5. symbolator symbolator Public

   Forked from kevinpt/symbolator

   Generate symbols from HDL components/modules

   Python 22 8

6. pyHDLParser pyHDLParser Public

   Forked from kevinpt/hdlparse

   Simple Python parser for extracting HDL (VHDL or Verilog) documentation

   Python 24 12