rust-minidump · msirringhaus · Mar 16, 2022 · Mar 15, 2022 · Mar 15, 2022 · Mar 16, 2022
@@ -26,9 +26,9 @@ impl CrashContext {
 
         {
             let fs = &self.inner.float_state;
-            out.float_save.fpsr = fs.fpsr;
-            out.float_save.fpcr = fs.fpcr;
-            out.float_save.regs[..FP_REG_COUNT].copy_from_slice(&fs.vregs[..FP_REG_COUNT]);
+            out.fpsr = fs.fpsr;
+            out.fpcr = fs.fpcr;
+            out.float_regs[..FP_REG_COUNT].copy_from_slice(&fs.vregs[..FP_REG_COUNT]);
         }
     }
 }
@@ -1,41 +1,47 @@
 use super::CrashContext;
-use crate::minidump_cpu::imp::*;
 use crate::minidump_cpu::RawContextCPU;
 
 impl CrashContext {
     pub fn get_instruction_pointer(&self) -> usize {
-        self.context.uc_mcontext.arm_pc as usize
+        self.inner.context.uc_mcontext.arm_pc as usize
     }
 
     pub fn get_stack_pointer(&self) -> usize {
-        self.context.uc_mcontext.arm_sp as usize
+        self.inner.context.uc_mcontext.arm_sp as usize
     }
 
     pub fn fill_cpu_context(&self, out: &mut RawContextCPU) {
-        out.context_flags = MD_CONTEXT_ARM_FULL;
-        out.iregs[0] = self.context.uc_mcontext.arm_r0;
-        out.iregs[1] = self.context.uc_mcontext.arm_r1;
-        out.iregs[2] = self.context.uc_mcontext.arm_r2;
-        out.iregs[3] = self.context.uc_mcontext.arm_r3;
-        out.iregs[4] = self.context.uc_mcontext.arm_r4;
-        out.iregs[5] = self.context.uc_mcontext.arm_r5;
-        out.iregs[6] = self.context.uc_mcontext.arm_r6;
-        out.iregs[7] = self.context.uc_mcontext.arm_r7;
-        out.iregs[8] = self.context.uc_mcontext.arm_r8;
-        out.iregs[9] = self.context.uc_mcontext.arm_r9;
-        out.iregs[10] = self.context.uc_mcontext.arm_r10;
+        out.context_flags =
+            crate::minidump_format::format::ContextFlagsArm::CONTEXT_ARM_FULL.bits();
 
-        out.iregs[11] = self.context.uc_mcontext.arm_fp;
-        out.iregs[12] = self.context.uc_mcontext.arm_ip;
-        out.iregs[13] = self.context.uc_mcontext.arm_sp;
-        out.iregs[14] = self.context.uc_mcontext.arm_lr;
-        out.iregs[15] = self.context.uc_mcontext.arm_pc;
+        {
+            let mut iregs = &mut out.iregs;
+            let gregs = &self.inner.context.uc_mcontext;
+            iregs[0] = gregs.arm_r0;
+            iregs[1] = gregs.arm_r1;
+            iregs[2] = gregs.arm_r2;
+            iregs[3] = gregs.arm_r3;
+            iregs[4] = gregs.arm_r4;
+            iregs[5] = gregs.arm_r5;
+            iregs[6] = gregs.arm_r6;
+            iregs[7] = gregs.arm_r7;
+            iregs[8] = gregs.arm_r8;
+            iregs[9] = gregs.arm_r9;
+            iregs[10] = gregs.arm_r10;
 
-        out.cpsr = self.context.uc_mcontext.arm_cpsr;
+            iregs[11] = gregs.arm_fp;
+            iregs[12] = gregs.arm_ip;
+            iregs[13] = gregs.arm_sp;
+            iregs[14] = gregs.arm_lr;
+            iregs[15] = gregs.arm_pc;
 
+            out.cpsr = gregs.arm_cpsr;
+        }
+
+        // TODO: this todo has been in breakpad for years....
         // TODO: fix this after fixing ExceptionHandler
-        out.float_save.fpscr = 0;
-        out.float_save.regs = [0; MD_FLOATINGSAVEAREA_ARM_FPR_COUNT];
-        out.float_save.extra = [0; MD_FLOATINGSAVEAREA_ARM_FPEXTRA_COUNT];
+        //out.float_save.fpscr = 0;
+        //out.float_save.regs = [0; MD_FLOATINGSAVEAREA_ARM_FPR_COUNT];
+        //out.float_save.extra = [0; MD_FLOATINGSAVEAREA_ARM_FPEXTRA_COUNT];
     }
 }
@@ -81,26 +81,35 @@ fn parse_features(val: &str) -> u32 {
     // The ELF hwcaps are listed in the "Features" entry as textual tags.
     // This table is used to rebuild them.
     let cpu_features_entries = [
-        CpuFeaturesEntry::new("swp", MDCPUInformationARMElfHwCaps::HWCAP_SWP),
-        CpuFeaturesEntry::new("half", MDCPUInformationARMElfHwCaps::HWCAP_HALF),
-        CpuFeaturesEntry::new("thumb", MDCPUInformationARMElfHwCaps::HWCAP_THUMB),
-        CpuFeaturesEntry::new("bit26", MDCPUInformationARMElfHwCaps::HWCAP_26BIT),
-        CpuFeaturesEntry::new("fastmult", MDCPUInformationARMElfHwCaps::HWCAP_FAST_MULT),
-        CpuFeaturesEntry::new("fpa", MDCPUInformationARMElfHwCaps::HWCAP_FPA),
-        CpuFeaturesEntry::new("vfp", MDCPUInformationARMElfHwCaps::HWCAP_VFP),
-        CpuFeaturesEntry::new("edsp", MDCPUInformationARMElfHwCaps::HWCAP_EDSP),
-        CpuFeaturesEntry::new("java", MDCPUInformationARMElfHwCaps::HWCAP_JAVA),
-        CpuFeaturesEntry::new("iwmmxt", MDCPUInformationARMElfHwCaps::HWCAP_IWMMXT),
-        CpuFeaturesEntry::new("crunch", MDCPUInformationARMElfHwCaps::HWCAP_CRUNCH),
-        CpuFeaturesEntry::new("thumbee", MDCPUInformationARMElfHwCaps::HWCAP_THUMBEE),
-        CpuFeaturesEntry::new("neon", MDCPUInformationARMElfHwCaps::HWCAP_NEON),
-        CpuFeaturesEntry::new("vfpv3", MDCPUInformationARMElfHwCaps::HWCAP_VFPv3),
-        CpuFeaturesEntry::new("vfpv3d16", MDCPUInformationARMElfHwCaps::HWCAP_VFPv3D16),
-        CpuFeaturesEntry::new("tls", MDCPUInformationARMElfHwCaps::HWCAP_TLS),
-        CpuFeaturesEntry::new("vfpv4", MDCPUInformationARMElfHwCaps::HWCAP_VFPv4),
-        CpuFeaturesEntry::new("idiva", MDCPUInformationARMElfHwCaps::HWCAP_IDIVA),
-        CpuFeaturesEntry::new("idivt", MDCPUInformationARMElfHwCaps::HWCAP_IDIVT),
-        CpuFeaturesEntry::new("idiv", HWCAP_IDIV),
+        CpuFeaturesEntry::new("swp", MDCPUInformationARMElfHwCaps::HWCAP_SWP.bits()),
+        CpuFeaturesEntry::new("half", MDCPUInformationARMElfHwCaps::HWCAP_HALF.bits()),
+        CpuFeaturesEntry::new("thumb", MDCPUInformationARMElfHwCaps::HWCAP_THUMB.bits()),
+        CpuFeaturesEntry::new("bit26", MDCPUInformationARMElfHwCaps::HWCAP_26BIT.bits()),
+        CpuFeaturesEntry::new(
+            "fastmult",
+            MDCPUInformationARMElfHwCaps::HWCAP_FAST_MULT.bits(),
+        ),
+        CpuFeaturesEntry::new("fpa", MDCPUInformationARMElfHwCaps::HWCAP_FPA.bits()),
+        CpuFeaturesEntry::new("vfp", MDCPUInformationARMElfHwCaps::HWCAP_VFP.bits()),
+        CpuFeaturesEntry::new("edsp", MDCPUInformationARMElfHwCaps::HWCAP_EDSP.bits()),
+        CpuFeaturesEntry::new("java", MDCPUInformationARMElfHwCaps::HWCAP_JAVA.bits()),
+        CpuFeaturesEntry::new("iwmmxt", MDCPUInformationARMElfHwCaps::HWCAP_IWMMXT.bits()),
+        CpuFeaturesEntry::new("crunch", MDCPUInformationARMElfHwCaps::HWCAP_CRUNCH.bits()),
+        CpuFeaturesEntry::new(
+            "thumbee",
+            MDCPUInformationARMElfHwCaps::HWCAP_THUMBEE.bits(),
+        ),
+        CpuFeaturesEntry::new("neon", MDCPUInformationARMElfHwCaps::HWCAP_NEON.bits()),
+        CpuFeaturesEntry::new("vfpv3", MDCPUInformationARMElfHwCaps::HWCAP_VFPv3.bits()),
+        CpuFeaturesEntry::new(
+            "vfpv3d16",
+            MDCPUInformationARMElfHwCaps::HWCAP_VFPv3D16.bits(),
+        ),
+        CpuFeaturesEntry::new("tls", MDCPUInformationARMElfHwCaps::HWCAP_TLS.bits()),
+        CpuFeaturesEntry::new("vfpv4", MDCPUInformationARMElfHwCaps::HWCAP_VFPv4.bits()),
+        CpuFeaturesEntry::new("idiva", MDCPUInformationARMElfHwCaps::HWCAP_IDIVA.bits()),
+        CpuFeaturesEntry::new("idivt", MDCPUInformationARMElfHwCaps::HWCAP_IDIVT.bits()),
+        CpuFeaturesEntry::new("idiv", MDCPUInformationARMElfHwCaps::HWCAP_IDIV.bits()),
     ];
 
     let mut ehwc = 0;

@@ -133,7 +133,7 @@ type Result<T> = std::result::Result<T, WriterError>;
 
 impl MinidumpWriter {
     pub fn new(process: Pid, blamed_thread: Pid) -> Self {
-        MinidumpWriter {
+        Self {
             process_id: process,
             blamed_thread,
             minidump_size_limit: None,
@@ -169,8 +169,6 @@ impl MinidumpWriter {
         self
     }
 
-    // Has to be deactivated for ARM for now, as libc doesn't include ucontext_t for ARM yet
-    #[cfg(not(target_arch = "arm"))]
     pub fn set_crash_context(&mut self, crash_context: CrashContext) -> &mut Self {
         self.crash_context = Some(crash_context);
         self

@@ -46,28 +46,8 @@ pub fn write(
     buffer: &mut DumpBuf,
 ) -> Result<MDRawDirectory, errors::SectionExceptionStreamError> {
     let exception = if let Some(context) = &config.crash_context {
-        let sig_addr;
-        #[cfg(target_arch = "arm")]
-        {
-            // Not part of libc-crate, but thats how the Linux-variant does it
-            // and according to the systemheaders, android as well.
-            #[allow(non_camel_case_types)]
-            #[repr(C)]
-            struct siginfo_sigfault {
-                _si_signo: libc::c_int,
-                _si_errno: libc::c_int,
-                _si_code: libc::c_int,
-                si_addr: *mut libc::c_void,
-            }
+        let sig_addr = context.inner.siginfo.ssi_addr as u64;
 
-            sig_addr = unsafe {
-                (*(&context.siginfo as *const libc::siginfo_t as *const siginfo_sigfault)).si_addr
-            } as u64;
-        }
-        #[cfg(not(target_arch = "arm"))]
-        {
-            sig_addr = context.inner.siginfo.ssi_addr as u64;
-        }
         MDException {
             exception_code: context.inner.siginfo.ssi_signo as u32,
             exception_flags: context.inner.siginfo.ssi_code as u32,

@@ -1,11 +1,5 @@
 use super::{CommonThreadInfo, Pid};
-use crate::errors::ThreadInfoError;
-use crate::minidump_cpu::imp::{
-    MD_CONTEXT_ARM_FULL, MD_CONTEXT_ARM_GPR_COUNT, MD_FLOATINGSAVEAREA_ARM_FPEXTRA_COUNT,
-    MD_FLOATINGSAVEAREA_ARM_FPR_COUNT,
-};
-use crate::minidump_cpu::RawContextCPU;
-use libc;
+use crate::{errors::ThreadInfoError, minidump_cpu::RawContextCPU};
 use nix::sys::ptrace;
 
 type Result<T> = std::result::Result<T, ThreadInfoError>;
@@ -44,7 +38,7 @@ pub struct user_fpregs {
 #[repr(C)]
 #[derive(Debug, Eq, Hash, PartialEq, Copy, Clone, Default)]
 pub struct user_regs {
-    uregs: [libc::c_long; 18],
+    uregs: [u32; 18],
 }
 
 #[derive(Debug)]
@@ -82,18 +76,16 @@ impl ThreadInfoArm {
     }
 
     pub fn fill_cpu_context(&self, out: &mut RawContextCPU) {
-        out.context_flags = MD_CONTEXT_ARM_FULL;
-        for idx in 0..MD_CONTEXT_ARM_GPR_COUNT {
-            out.iregs[idx] = self.regs.uregs[idx] as u32;
-        }
+        out.context_flags =
+            crate::minidump_format::format::ContextFlagsArm::CONTEXT_ARM_FULL.bits();
+
+        out.iregs.copy_from_slice(&self.regs.uregs[..16]);
         // No CPSR register in ThreadInfo(it's not accessible via ptrace)
         out.cpsr = 0;
 
         #[cfg(not(target_os = "android"))]
         {
             out.float_save.fpscr = self.fpregs.fpsr as u64 | ((self.fpregs.fpcr as u64) << 32);
-            out.float_save.regs = [0; MD_FLOATINGSAVEAREA_ARM_FPR_COUNT];
-            out.float_save.extra = [0; MD_FLOATINGSAVEAREA_ARM_FPEXTRA_COUNT];
         }
     }
 

@@ -6,9 +6,8 @@ cfg_if::cfg_if! {
         pub type RawContextCPU = minidump_common::format::CONTEXT_X86;
         pub type FloatStateCPU = minidump_common::format::FLOATING_SAVE_AREA_X86;
     } else if #[cfg(target_arch = "arm")] {
-        pub mod arm;
-        pub use arm as imp;
-        pub type RawContextCPU = arm::MDRawContextARM;
+        pub type RawContextCPU = minidump_common::format::CONTEXT_ARM;
+        pub type FloatStateCPU = minidump_common::format::FLOATING_SAVE_AREA_ARM;
     } else if #[cfg(target_arch = "aarch64")] {
         /// This is the number of general purpose registers _not_ counting
         /// the stack pointer