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1. All-Digital-PVT-Sensor All-Digital-PVT-Sensor Public

   An all-digital PVT tracking sensor system for supply voltage droop tolerance in 45nm CMOS. Features a Dynamic Variation Monitor (DVM), tunable-length delay chain, and glitch-free adaptive clock gat…

   Verilog

2. 4x4-SRAM-Array-Design 4x4-SRAM-Array-Design Public

   Custom 4x4 SRAM memory array layout and post-layout simulation designed using Cadence Virtuoso (FreePDK45). Includes basic standard cell designs (MUX21, NAND2) in the appendix

   Standard ML

3. MNIST-NPU-ASIC MNIST-NPU-ASIC Public

   A complete ASIC design flow for a MNIST NPU. Features a quantized hardware-friendly architecture, SystemVerilog RTL implementation, and a verified backend-ready flow for logic synthesis and GDSII g…

   Verilog 1

4. FM_Radio_Project FM_Radio_Project Public

   FM Radio receiver & stereo decoder in SystemVerilog. Fully pipelined architecture achieving 102.3 MHz timing closure on FPGA. Featured optimizations: 32-stage restoring divider, staged FIR adder tr…

   SystemVerilog

5. Snake-RL-Benchmarks Snake-RL-Benchmarks Public

   A rigorous RL benchmark project on Snake. Features a comprehensive comparison of Online RL (Q-Learning, SARSA, DQN, PPO) vs. Offline Imitation Learning (Behavior Cloning) with detailed ablation stu…

   Jupyter Notebook

6. NU_CE387_FPGA-Design NU_CE387_FPGA-Design Public

   Real-Time Digital Systems Design & Verification with FPGAs (CE387). Featuring SystemVerilog RTL design, UVM methodology, and complete EDA flow using ModelSim, Synplify Pro, and Cadence Innovus.

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